1. Field of the Invention
The present invention relates generally to a method of fabricating an integrated circuit, and more specifically to a method of fabricating an integrated circuit relating to the alignment of photoresist patterns.
2. Description of the Prior Art
In the fabrication of semiconductor integrated circuits (ICs), semiconductor devices are connected by several metallic interconnecting layers commonly referred to as multi-level interconnects. A damascene process is a convenient and predominant method for forming the multi-level interconnects. The damascene process includes etching a dielectric material layer to form trench and/or via patterns, filling the patterns with conductive materials such as copper, and performing a planarization process. Thus a metal interconnect is obtained.
Photolithography is an essential process in the fabrication of semiconductor ICs. Principally, photolithography forms designed patterns such as implantation patterns or layout patterns on at least a reticle, and then precisely transfers such pattern to a photoresist layer by exposure and development steps. Subsequently, by performing semiconductor processes such as ion implantation, etching processes, or deposition, the complicated and sophisticated IC structure is obtained.
With the miniaturization of semiconductor devices and corresponding progress in fabrication methods, conventional lithography processes have met a bottleneck due to printability and manufacturability. To meet the requirements of device design rules which continue to push the resolution limits of existing processes and tooling, a double patterning technique (DPT) has been developed. This is one of the most promising lithography technologies for 32 nanometer (nm) node and 22 nm node patterning since it can increase the half-pitch resolution by up to 200% using current infrastructures.